Level shifting circuits can translate an input signal that varies within one voltage range, to an output signal that varies within another, different voltage range. Typically, level shifting circuits can be utilized to translate between logic signals operating at different signal voltage levels (e.g., TTL to CMOS). Level shifting circuits for metal-oxide-semiconductor (MOS) type technologies, particularly CMOS type technology are well known.
Co-pending U.S. patent application Ser. No. 11/452,442 filed on Jun. 13, 2006 and U.S. Provisional Patent Application Ser. No. 60/799,787 filed on May 11, 2006, both by Ashok K. Kapoor, show examples of novel circuits that include junction field effect transistors (JFETs) that operate at relatively low voltage levels (e.g., 0 to +0.5 volts). Such circuits can form integrated circuits that include few, or preferably no MOS type transistors. JFET transistors may have manufacturing advantages over MOSFETs due to the lack of a thin gate oxide layer. Accordingly, CMOS type level shifting circuits are of no benefit in shifting voltage levels of signals in a device that includes only JFET technology.
Co-pending U.S. patent application Ser. No. 11/495,099 filed on Jul. 28, 2006 and U.S. Provisional Patent Application Ser. No. 11/495,908 filed on Jul. 28, 2006, both by the present applicants, show examples of novel level shift circuits that include junction field effect transistors (JFETs). U.S. patent application Ser. No. 11/495,099 shows level shift circuits having complementary JFETs that may shift from a relatively low voltage level (e.g., 0 to +0.5 volts) to a relatively high voltage level (e.g., 0 to +2.5 volts).